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HY628100A Series
128Kx8bit CMOS SRAM
DESCRIPTION
The HY628100A is a high speed, low power and 1M bit CMOS Static Random Access Memory organized as 131,072 words by 8bit. The HY628100A uses high performance CMOS process technology and designed for high speed low power circuit technology. It is particulary well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0V. Product Voltage Speed Operation No (V) (ns) Current(mA) HY628100A 5.0 55/70/85 10 Comment : 50ns is available with 30pF test load.
FEATURES
* Fully static operation and Tri-state output * TTL compatible inputs and outputs * Battery backup(L/LL-part) - 2.0V(min) data retention * Standard pin configuration - 32pin 525mil SOP - 32pin 8x20mm TSOP-I(Standard)
Standby Current(uA) L LL 1mA 100 20
Temperature (C) 0~70
PIN CONNECTION
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 CS2 /WE A13 A8 A9 A11 /OE A10 /CS1 I/O8 I/O7 I/O6 I/O5 I/O4
A11 A9 A13 /WE CS2 A15 Vcc NC A16 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 11 12 13 14 15 16
32 30 29 28 27 26 25 24 22 21 20 19 18 17
/OE /CS1 DQ8 DQ7 DQ6 DQ5 DQ4 Vss DQ3 DQ1 A0 A1 A2 A3
SOP
TSOP-I(Standard)
PIN DESCRIPTION
Pin Name /CS1 CS2 /WE /OE A0 ~ A16 I/O1 ~ I/O8 Vcc Vss Pin Function Chip Select 1 Chip Select 2 Write Enable Output Enable Address Input Data Input/Output Power(5.0V) Ground
BLOCK DIAGRAM
SENSE AMP A0 ADD INPUT BUFFER COLUMN DECODER ROW DECODER I/O1 OUTPUT BUFFER I/O8
A16 CONTROL LOGIC /CS1 CS2 /OE /WE
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.05 /Feb.99 Hyundai Semiconductor
WRITE DRIVER
MEMORY ARRAY 1024x1024
HY628100A Series
ORDERING INFORMATION
Part No. Speed Power HY628100AG 55/70/85 HY628100ALG 55/70/85 L-part HY628100ALLG 55/70/85 LL-part HY628100AT1 55/70/85 HY628100ALT1 55/70/85 L-part HY628100ALLT1 55/70/85 LL-part Comment : 50ns is available with 30pF test load. Temp Package SOP SOP SOP TSOP-I(Standard) TSOP-I(Standard) TSOP-I(Standard)
ABSOLUTE MAXIMUM RATING (1)
Symbol Vcc, VIN, VOUT TA TSTG PD IOUT TSOLDER Parameter Power Supply, Input/Output Voltage Operating Temperature Storage Temperature Power Dissipation Data Output Current Lead Soldering Temperature & Time Rating -0.5 to 7.0 0 to 70 -65 to 125 1.0 50 260 *10 Unit V C C W mA C*sec
Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliablity.
RECOMMENDED DC OPERATING CONDITION
TA=0C to 700C /-400C to 85C Symbol Parameter Min. Vcc Supply Voltage 4.5 Vss Ground 0 VIH Input High Voltage 2.2 VIL Input Low Voltage -0.5(1) Note : 1. VIL = -3.0V for pulse width less than 30ns Typ. 5.0 0 Max. 5.5 0 Vcc+0.5 0.8 Unit V V V V
TRUTH TABLE
/CS1 H X L L L CS2 X L H H H /WE X X H H L /OE X X H L X MODE Standby Output Disabled Read Write I/O OPERATION High-Z High-Z High-Z Data Out Data In
Note : 1. H=VIH, L=VIL, X=don't care
Rev.05 /Feb.99
2
HY628100A Series
DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V10%, TA = 0C to 70C, unless otherwise specified Symbol Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc ILO Output Leakage Current Vss < VOUT < Vcc, /CS1 = VIH or CS2 = VIL or /OE = VIH or /WE = VIL Icc Operating Power Supply /CS1 = VIL, CS2 = VIH, Current VIN = VIH or VIL, II/O = 0mA ICC1 Average Operating /CS1 = VIL CS2 = VIH, Current Min Duty Cycle = 100%, II/O = 0mA ISB TTL Standby Current /CS1 = VIH or CS2 = VIL (TTL Input) ISB1 Standby Current /CS1 > Vcc - 0.2V (CMOS Input) CS2 > 0.2V or L CS2 > Vcc - 0.2V LL VOL Output Low Voltage IOL = 2.1Ma VOH Output High Voltage IOH = -1mA Note : Typical values are at Vcc = 5.0V, TA = 25C Min. -1 -1 2.4 Typ. 5 30 1 2 1 Max. 1 1 10 50 2 1 100 20 0.4 Unit uA uA mA mA mA mA uA uA V V
AC CHARACTERISTICS
Vcc = 5.0V10%, TA = 0C to 70C (Normal), unless otherwise specified -55 -70 # Symbol Parameter Min. Max. Min. Max. READ CYCLE 1 TRC Read Cycle Time 55 70 2 tAA* Address Access Time 55 70 3 tACS* Chip Select Access Time 55 70 4 TOE Output Enable to Output Valid 25 35 5 TCLZ Chip Select to Output in Low Z 10 10 6 TOLZ Output Enable to Output in Low Z 5 5 7 tCHZ Chip Deselection to Output in High Z 0 20 0 25 8 tOHZ Out Disable to Output in High Z 0 20 0 25 9 tOH Output Hold from Address Change 10 10 WRITE CYCLE 10 tWC Write Cycle Time 55 70 11 tCW Chip Selection to End of Write 45 60 12 tAW Address Valid to End of Write 45 60 13 tAS Address Set-up Time 0 0 14 tWP Write Pulse Width 40 50 15 tWR Write Recovery Time 0 0 16 tWHZ Write to Output in High Z 0 20 0 25 17 tDW Data to Write Time Overlap 25 30 18 tDH Data Hold from Write Time 0 0 19 tOW Output Active from End of Write 5 5 Comment : tAA* and tACS* can meet 50ns with 30pF test load. -85 Max. 85 85 45 30 30 30 -
Min 85 10 5 0 0 10 85 70 70 0 55 0 0 35 0 5
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Rev.05 /Feb.99
3
HY628100A Series
AC TEST CONDITIONS
TA = 0C to 70C (Normal), unless otherwise specified PARAMETER Value Input Pulse Level 0.8V to 2.4V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load CL = 100pF + 1TTL Load CL* = 30pF + 1TTL Load Comment * : Test load is 30pF for 50ns
AC TEST LOADS
TTL
CL(1)
Note : Including jig and scope capacitance
CAPACITANCE
Temp = 25C, f= 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF
Note : These parameters are sampled and not 100% tested
Rev.05 /Feb.99
4
HY628100A Series
TIMING DIAGRAM
READ CYCLE 1
tRC ADDR tAA OE tOE tOLZ CS1 tOH
CS2 tACS tCLZ Data Out High-Z Data Valid tOHZ tCHZ
Note(READ CYCLE): 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for the read cycle.
READ CYCLE 2
tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH
Note(READ CYCLE): 1. /WE is high for the read cycle. 2. Device is continuously selected /CS1 = VIL, CS2 = VIH. 3. /OE =VIL.
Rev.05 /Feb.99
5
HY628100A Series
WRITE CYCLE 1(/WE Controlled)
tWC ADDR tAW tCW CS1 tWR
CS2 tAS WE tWP
tDW Data In tOHZ Data Out Data Undefined
tDH Data Valid tOW High-Z
WRITE CYCLE 2 (/CS1 Controlled)
tWC ADDR tAS tCW CS1 tAW CS2 tWP WE tWR
tDW Data In High-Z Data Valid tCLZ tWHZ Data Out High-Z
tDH
High-Z
Rev.05 /Feb.99
6
HY628100A Series
WRITE CYCLE 3 (CS2 Controlled)
tWC ADDR tAS tCW CS1 tAW CS2 tWP WE tWR
tDW Data In
High-Z
tDH
Data Valid tCLZ tWHZ
Data Out
High-Z
High-Z
Notes(WRITE CYCLE): 1. A write occurs during the overlap of a low /CS1, CS2 and low /WE. A write begines at the latest transition among /CS1 going low, CS2 going high and /WE going low: A write ends at the earliest transition among /CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of write to the end of write. . 2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write . 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS1, or /WE going high, and tWR is applied in case a write ends at CS2 going low. 5. If /OE, CS2 and /WE are in the read mode during this period, the I/O pins are in the output low-Z state, input of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state. 7. Dout is the read data of the new address. 8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite phase leading to the outputs should not be applied.
Rev.05 /Feb.99
7
HY628100A Series
DATA RETENTION ELECTRIC CHARACTERISTIC
SYM VDR Parameter Vcc for Data Retention Test Condition /CS1 > Vcc - 0.2V CS2 < 0.2V or > Vcc - 0.2V, VssVcc - 0.2V CS2< 0.2V or > Vcc - 0.2V, VssICCDR
L LL
0 tRC(2)
2 1 -
50 10 -
uA uA ns ns
tCDR tR
Notes: 1. Typical values are under the condition of TA = 25C. 2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM 1
DATA RETENTION MODE tCDR tR
VCC 4.5V
2.2V VDR CS1>VCC-0.2V CS1 VSS
DATA RETENTION TIMING DIAGRAM 2
DATA RETENTION MODE tCDR tR
VCC 4.5V CS2 VDR
0.4V VSS
CS2<0.2V
Rev.05 /Feb.99
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HY628100A Series
RELIABILITY SPEC.
TEST MODE ESD HBM MM LATCH - UP TEST SPEC. > 2000V > 250V < -100mA > 100mA
PACKAGE INFORMATION
32pin 525mil Small Outline Package(G)
UNIT : INCH(mm)
0.810(20.574) 0.804(20.422)
0.444(11.278) 0.438(11.125) 0.564(14.326) 0.546(13.868)
0.109(2.769) 0.099(2.515) 0.011(0.279) 0.004(0.102) 0.050(1.27)BSC 0.020(0.508) 0.014(0.356) 0 deg 8 deg 0.0425(1.080) 0.0235(0.597)
0.0125(0.318) 0.0061(0.155)
32pin 8x20mm Thin Small Outline Package Standard(T1)
#1
#32 0.319(8.103) 0.311(7.900) UNIT : INCH(mm)
#16 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914)
#17
0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) 0.025(0.64) 0.021(0.54) 0.008(0.21) 0.004(0.10) 0.020(0.50) BSC 0.011(0.27) 0.007(0.17)
Rev.05 /Feb.99
9

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